Samsung Electronics Reaches Technical Barrier in Refining Line Width of DRAM


Samsung Electronics has established a roadmap for its processes after 18-nano process that reduces line width of DRAM by a unit of one nanometer. Compared to how line width was greatly reduced by 5 to 10 nanometers for 40-nano processes and 2 to 3 nanometers for 20-nano processes, speed of refinement has been visibly slowed down. This indicates that technical barrier for refinement has become higher.

It seems that prices of DRAMs will become stabilized even more as speed of expansion of output of DRAMs has slowed down and that there will be ‘paradoxical phenomenon of refinement’ where booming of semiconductor industries will continue. On the other hand, it is likely that Samsung Electronics’ strategy of widening gap in productivity with its competitors through refinement of processes will hit its limit. Some are even worried that this will allow newcomers such as China to catch up to Samsung Electronics. Industries predict that 15-nano process will be the destination of refinement of DRAM.

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According to industries on the 17th, Samsung Electronics is currently developing 17-nano DRAM (Armstrong) as the next-generation product that will follow 18-nano DRAM (name of development code: Pascal) that was mass-produced by Samsung Electronics since last year. It is planning to finish development by end of this year and mass-produce 17-nano DRAM sometime during next year. Samsung Electronics has also established a development team for 16-nano DRAM (Kevlar) which will be mass-produced in 2020 at the earliest. Participants of this project explain that this schedule can be postponed which indicates that it is that much difficult to implement this technology. Current Samsung Electronics’ main node of DRAM production is 20-nano DRAM (Boltzmann). It is going to gradually increase percentage of 18-nano DRAMs that are produced this year and has established a goal to have 18-nano DRAM as its major product starting from next year.

Samsung Electronics has refined its DRAM’s 20-nano-range processes from 28-nano to 25-nano to 20-nano DRAM. Due to instable yield of 25-nano DRAMs, it had to mass-produce 23-nano products which were produced through a modified process. It had decreased line width about 10 to 20%.

Picture of Samsung Electronics’ 8GB LPDDR4 Mobile DRAM that was introduced last year.  DRAM die within a package was made through 18-nano process.  Samsung Electronics is planning to upgrade its process from 18-nano to 17-nano to 16-nano sequentially in the future.

Picture of Samsung Electronics’ 8GB LPDDR4 Mobile DRAM that was introduced last year. DRAM die within a package was made through 18-nano process. Samsung Electronics is planning to upgrade its process from 18-nano to 17-nano to 16-nano sequentially in the future.

As it started producing 10-nano-range DRAMs, it has reduced line width at a slower speed. 17-nano DRAMs do not use processes and materials that are huge different from the ones that are used for 18-nano DRAMs. However certain changes can occur to a structure of a cell in order to secure space for a capacitor that saves electric charges. There will be huge changes to patterning method starting with 16-nano processes and Samsung Electronics is planning to use EUV (Extreme Ultraviolet) exposure equipment to draw certain important patterns.

Samsung Electronics has not established a development team for processes that are lower than 15-nano process yet. Currently there is only a framework for an agreement. Starting with these processes, there will be more leakage of current and interference phenomenon for capacitors. To prevent them effectively, Samsung Electronics is planning to use new high dielectric (High-K) deposition material instead of zirconium that is used currently. It is currently carrying out R&D on materials that are seen as possible candidates and is keeping them secret.

“After 1x (18-nano), 1y (17-nano), and 1z (16-nano), node of process will be reduced to 1a, 1b, 1c, and 1d.” said Manager Jung Eun-seung of Samsung Electronics Device Solution (DS) Sector’s Semiconductor Laboratory. “In order to continue to decrease line width, we need to develop new materials that are different from current materials and increase stability of processes in order to introduce them to mass-production lines.”

Higher technical barrier for DRAM processes is likely to have positive effects on market situations since expansion of supplies will also slow down. This is so-called ‘paradox of refinement of processes’ according to experts in memories. Cycles of booming and slump had come with regularity every two to three years as refinement of processes and new investments had taken place side by side. However now there is no reason for carrying out new investments by force as number of DRAM suppliers has been narrowed down to Samsung Electronics, SK Hynix, and Micron and as prices will only drop if amount of supplies is increased. Due to this reason, they are only working on refining processes that can lower production cost. Current investments into DRAMs are mostly made to offset increase in number of processes that occur due to refinement of process. 

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“Booming of DRAM will continue if there aren’t any major changes to markets and technologies.” said a representative for an industry. “However we cannot slack off on R&D in order to not give any rooms to Chinese companies that have enormous funding from Chinese Government and are looking to enter markets for DRAM.”

Staff Reporter Han, Juyeop |

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